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Modeling and Design for Low Power and Variation Tolerance in Integrated Circuits

Akella Kamakshi, Divya
Thesis/Dissertation; Online
Akella Kamakshi, Divya
Calhoun, Benton
Modern integrated circuits (ICs) ranging from ultra-low power (ULP) internet-of-things (IoT) devices to high-performance (HP) processors, cater to a wide spectrum of applications and notably aid in revolutionizing human life-style. To cite a few instances, wearable technology is a ubiquitous IoT application that has made great strides in the health-care and fitness domain, HP chips such as graphics processing units enable an efficient computation platform for various scientific applications, etc. However, together with an ever-increasing scope of applications that ICs like these can support, they are also faced with a multitude of design challenges. In this work, we aim to address two such design challenges namely power consumption and tolerance to circuit or environmental variations. Low-power operation is a crucial requirement in modern IC design. In self or battery-powered IoT devices that are required to have a long lifetime, ULP design is of utmost importance due to limited battery capacities and efficiency of current energy harvesting technologies. In the HP domain, low power is necessary in portable devices such as tablets and laptops, and to reduce the need for heat-sinks to cool thermal hot-spots in processors. Tolerance to the effects of process and environmental variations are also crucial to both ULP and HP designs. In ULP designs, a critical obstacle to lowering the supply voltage to reduce power, is the increased sensitivity of circuits to process, voltage, and temperature variations. These variations affect circuit delays and limit product yield. Similarly, in HP designs, performance can be degraded due to workload variations that can cause power supply noise and temperature gradients. Toward the above goals of lowering power and tolerating variations, we explore design techniques for self-powered, IoT chips that provide a flexible platform capable of gathering, processing, and transmitting data. We specifically target reliable and ULP circuits for data and clocking. We build a modeling framework to enable variation tolerance analysis of ULP and HP ICs. In the ULP domain, we analyze the potential of a post-silicon hold time closure technique to overcome the impact of variations in digital circuits. In the HP domain, we analyze the potential of a fine-grained GALS scheme to overcome the effects of power supply noise. We also present designs of a temperature sensor and a supply voltage monitor, which are crucial to enabling variation tolerance in ULP chips. Finally, we delve into a tool-flow to make the design of variation tolerant digital components feasible.
University of Virginia, Department of Electrical Engineering, PHD (Doctor of Philosophy), 2017
Published Date
PHD (Doctor of Philosophy)
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