Item Details

High-Speed CMOS Circuits for Optical Receivers

Jafar Savoj, Behzad Razavi
Format
Book
Published
Boston : Kluwer Academic Publishers, c2001.
Language
English
ISBN
079237388X (alk. paper)
Contents
  • 1.1 Overview of the Fiber Optic Network 3
  • 1.2 Overview of Fiber Optic Transceivers 5
  • 2. Tias and Limiters 13
  • 3. Clock and Data Recovery Architectures 21
  • 3.1 Open-Loop CDR Architectures 22
  • 3.2 Phase-Locking CDR Architectures 23
  • 3.2.1 Full-Rate and Half-Rate Architectures 27
  • 3.2.2 Oscillators 29
  • 3.2.2.1 General Theory 29
  • 3.2.2.2 Ring Oscillators 30
  • 3.2.2.3 LC Oscillators 32
  • 3.2.2.4 PLL Jitter Calculation 41
  • 3.2.3 Phase Detectors 42
  • 3.2.3.1 Linear Phase Detectors 45
  • 3.2.3.2 Binary Phase Detectors 48
  • 3.2.4 Frequency Detectors 52
  • 3.2.4.1 Referenced Frequency Detectors 53
  • 3.2.4.2 Referenceless Frequency Detectors 55
  • 3.2.5 Decision Circuits 58
  • 4. A Cmos Interface for Detection of 1.2-GB/S Rz Data 61
  • 4.2 Matched Filtering 62
  • 4.3 Architecture 65
  • 4.4 Building Blocks 67
  • 4.4.1 Low-Noise Wideband Amplifier 67
  • 4.4.2 Integrate-and-Dump Circuit 69
  • 4.4.3 Demultiplexer 71
  • 4.4.4 Clock Buffer 73
  • 4.5 Experimental Results 74
  • 5. A 10-GB/S Linear Half-Rate Coms CDR Circuit 77
  • 5.1 Architecture 77
  • 5.2 Building Blocks 80
  • 5.2.1 VCO 80
  • 5.2.2 Phase Detector 83
  • 5.2.3 Charge Pump and Loop Filter 87
  • 5.3 Experimental Results 89
  • 6. A 10-GB/S Cmos CDR Circuit with Wide Capture Range 95
  • 6.2 Architecture 97
  • 6.3 Building Blocks 98
  • 6.3.1 VCO 98
  • 6.3.2 Phase and Frequency Detector 102
  • 6.3.3 Charge Pump 106
  • 6.3.4 Output Buffers 107
  • 6.4 Loop Characterization 108
  • 6.5 Experimental Results 109.
Description
xiv, 124 p. : ill. ; 25 cm.
Notes
Includes bibliographical references (p. [119]-122) and index.
Technical Details
  • Access in Virgo Classic

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    g| 1.1 t| Overview of the Fiber Optic Network g| 3 -- g| 1.2 t| Overview of Fiber Optic Transceivers g| 5 -- g| 2. t| Tias and Limiters g| 13 -- g| 3. t| Clock and Data Recovery Architectures g| 21 -- g| 3.1 t| Open-Loop CDR Architectures g| 22 -- g| 3.2 t| Phase-Locking CDR Architectures g| 23 -- g| 3.2.1 t| Full-Rate and Half-Rate Architectures g| 27 -- g| 3.2.2 t| Oscillators g| 29 -- g| 3.2.2.1 t| General Theory g| 29 -- g| 3.2.2.2 t| Ring Oscillators g| 30 -- g| 3.2.2.3 t| LC Oscillators g| 32 -- g| 3.2.2.4 t| PLL Jitter Calculation g| 41 -- g| 3.2.3 t| Phase Detectors g| 42 -- g| 3.2.3.1 t| Linear Phase Detectors g| 45 -- g| 3.2.3.2 t| Binary Phase Detectors g| 48 -- g| 3.2.4 t| Frequency Detectors g| 52 -- g| 3.2.4.1 t| Referenced Frequency Detectors g| 53 -- g| 3.2.4.2 t| Referenceless Frequency Detectors g| 55 -- g| 3.2.5 t| Decision Circuits g| 58 -- g| 4. t| A Cmos Interface for Detection of 1.2-GB/S Rz Data g| 61 -- g| 4.2 t| Matched Filtering g| 62 -- g| 4.3 t| Architecture g| 65 -- g| 4.4 t| Building Blocks g| 67 -- g| 4.4.1 t| Low-Noise Wideband Amplifier g| 67 -- g| 4.4.2 t| Integrate-and-Dump Circuit g| 69 -- g| 4.4.3 t| Demultiplexer g| 71 -- g| 4.4.4 t| Clock Buffer g| 73 -- g| 4.5 t| Experimental Results g| 74 -- g| 5. t| A 10-GB/S Linear Half-Rate Coms CDR Circuit g| 77 -- g| 5.1 t| Architecture g| 77 -- g| 5.2 t| Building Blocks g| 80 -- g| 5.2.1 t| VCO g| 80 -- g| 5.2.2 t| Phase Detector g| 83 -- g| 5.2.3 t| Charge Pump and Loop Filter g| 87 -- g| 5.3 t| Experimental Results g| 89 -- g| 6. t| A 10-GB/S Cmos CDR Circuit with Wide Capture Range g| 95 -- g| 6.2 t| Architecture g| 97 -- g| 6.3 t| Building Blocks g| 98 -- g| 6.3.1 t| VCO g| 98 -- g| 6.3.2 t| Phase and Frequency Detector g| 102 -- g| 6.3.3 t| Charge Pump g| 106 -- g| 6.3.4 t| Output Buffers g| 107 -- g| 6.4 t| Loop Characterization g| 108 -- g| 6.5 t| Experimental Results g| 109.
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