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WM FIFOs: Size Analysis

Wulf, Wm; Wad, Rohit
Format
Report
Author
Wulf, Wm
Wad, Rohit
Abstract
The WM computer architecture interposes data FIFOs between the execution units and memory. Data FIFOs improve performance by permitting memory delays to be overlapped with instruction execution. The depth of a FIFO depends on the average rate of memory accesses and the proximity of references to the FIFO. This project aims at exploring the effect of FIFO depth on performance, and suggesting a size that would be suitable for most applications. Note: Abstract extracted from PDF file via OCR
Language
English
Date Received
2012-10-29
Published
University of Virginia, Department of Computer Science, 1991
Published Date
1991
Collection
Libra Open Repository
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