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A Discussion on the Thermal Benefit of Multicore Floorplanning at the Microarchitectural Level

Sankaranarayanan, Karthik; Stan, Mircea; Skadron, Kevin
Format
Report
Author
Sankaranarayanan, Karthik
Stan, Mircea
Skadron, Kevin
Abstract
This paper presents research to address the temperature challenge in multicore processors through the lever of thermally-aware floorplanning. Specifically, it examines the thermal benefit in a variety of placement choices available in a multicore processor including alternative core orientation and insertion of L2 cache banks between cores as cooling buffers. In comparison with an idealized scheme that scatters the functional blocks of a multicore across the entire chip area to maximize uniformity, a combination of core orientation and L2 cache bank insertion achieves about 75% of the peak temperature reduction with negligible performance impact. On an average, the improvement in temperature is about 20% of the magnitude above the ambient temperature.
Language
English
Date Received
2012-10-29
Published
University of Virginia, Department of Computer Science, 2009
Published Date
2009
Rights
All rights reserved (no additional license for public reuse)
Collection
Libra Open Repository

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