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Improving Instruction-Level Parallelism by Loop Unrolling and Dynamic Memory Disambiguation

Davidson, Jack; Jinturkar, Sanjay
Format
Report
Author
Davidson, Jack
Jinturkar, Sanjay
Abstract
Exploitation of instruction-level parallelism is an effective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism. This paper describes and evaluates a software technique, dynamic memory disambiguation, that permits loops containing loads and stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism. The results of our evaluation show that when dynamic memory disambiguation is applied in conjunction with loop unrolling, register renaming, and static memory disambiguation, the ILP of memory-intensive benchmarks can be increased by as much as 300 percent over loops where dynamic memory disambiguation is not performed. Our measurements also indicate that for the programs that benefit the most from these optimizations, the register usage does not exceed the number of registers on most high-performance processors.
Language
English
Date Received
2012-10-29
Published
University of Virginia, Department of Computer Science, 1995
Published Date
1995
Collection
Libra Open Repository
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