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Power and Thermal Effects of SRAM vs. Latch-Mix Design Styles and Clock Gating Choices

Li, Yingmin; Skadron, Kevin
Li, Yingmin
Skadron, Kevin
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of power dissipation, and both design styles and various clock gating schemes can be found in modern, high-performance proces- sors. Although some work in the circuits domain has explored these issues from a power perspective, thermal treatments are less common, and we are not aware of any work in the archi- tecture domain. We study both SRAM and latch and multiplexor (�latch- mux�) designs and their associated clock-gating options. Us- ing circuit-level simulations of both design styles, we derive power-dissipation ratios which are then used in cycle-level power/performance/thermal simulations. We find that even though the �unconstrained� power of SRAM designs is al- ways better than latch-mux designs, latch-mux designs dissi- pate less power in practice when a structure�s average occu- pancy is low but access rate is high, especially when �stall gat- ing� is used to minimize switching power. We also find that latch-mux designs with stall gating are especially promising from a thermal perspective, because they exhibit lower power density than SRAM designs. Overall, when combined with implementation and verification challenges for SRAMs, latch- mux designs with stall gating appear especially promising for designs with thermal constraints. This paper also shows the importance of considering architectural effects, as well as the importance for thermal simulation of considering lower-level circuit-design choices.
University of Virginia, Department of Computer Science, 2005
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