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A Parallel VLSI Circuit Layout Methodology

Bapat, S; Cohoon, J
Format
Report
Author
Bapat, S
Cohoon, J
Abstract
We propose a parallel computation layout technique that solves the layout problem directly rather than decomposing it into the traditional distinct steps of placement and routing. The method combines a superior geometric partitioning algorithm with extensive use of pre~con1puted minimum - length Steiner trees to produce layouts. Note: Abstract extracted from PDF file via OCR
Language
English
Date Received
2012-10-29
Published
University of Virginia, Department of Computer Science, 1992
Published Date
1992
Collection
Libra Open Repository
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