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The WM Computer Architectures: Military Standard Manual

Jones, Anita; Wad, Rohit
Format
Report
Author
Jones, Anita
Wad, Rohit
Abstract
This report is a military standard definition of the instruction set of the WM family of computer architectures. The WM instruction set architecture supports microconcurrency at the instruction level; i.e. it facilitates the execution of several scalar instructions concurrently. Also, WM supports vector processing; that is, it has single instructions that apply the same operation to a collection of data items. Another interesting feature of the WM architectures is streaming - - a mechanism for asynchronous loads and stores of "vector - like" data, that is, data with a known dispiacement between successive items. This facility applies to WM's scalar as well as its vector execution units, and has the effect of potentially executing many load/store operations concurrent with the execution of other instructions. The report has been patterned after the 1750 military standard manual. Note: Abstract extracted from PDF file via OCR
Language
English
Date Received
2012-10-29
Published
University of Virginia, Department of Computer Science, 1990
Published Date
1990
Collection
Libra Open Repository
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