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A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs

Landon, T; Salinas, M; Klenke, R; Aylor, J; McKee, S; Wright, K
Format
Report
Author
Landon, T
Salinas, M
Klenke, R
Aylor, J
McKee, S
Wright, K
Abstract
This paper describes the design process used in developing a Stream Memory Controller (SMC)*. The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75mm process and has been tested at 36MHz.
Language
English
Date Received
2012-10-29
Published
University of Virginia, Department of Computer Science, 1995
Published Date
1995
Collection
Libra Open Repository
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