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Performance of the IPSC/860 Node Architecture

Moyer, Steven
Format
Report
Author
Moyer, Steven
Abstract
Intel's iPSC/860 hypercube is the latest in a series of message-passing multicomputers. The performance of individual iPSC/860 computational nodes is the focus of this report; in particular, the performance of basic computational kernels common in scientific computing is examined. Understanding the operation of the iPSC/860 node memory system is key to achieving maximum node performance; from a comprehensive study of the processor-memory interrelationship, guidelines are established for implementing operations in a manner consistent with the processor architecture and memory system performance characteristics. It is demonstrated that the iPSC/860 node architecture exhibits a basic imbalance between processor speed and memory system bandwidth; due to this imbalance, even for highly optimized hand-coded routines the average performance of basic computational kernels can be as much as an order of magnitude below peak processor rate. Note: Abstract extracted from PDF text
Language
English
Date Received
2012-10-30
Published
University of Virginia, Institute for Parallel Computation, 1991
Published Date
1991
Rights
All rights reserved (no additional license for public reuse)
Collection
Libra Open Repository

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