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Improving Reliability and Power Consumption of Memories in Battery-Less Systems-on-Chip

Yahya, Farah
Thesis/Dissertation; Online
Yahya, Farah
Calhoun, Benton
Recent projections by Cisco have suggested that more than 50 billion devices are expected to sense, process and transmit information as part of the internet of things (IoT) by 2020. These devices will target a wide range of applications including but not limited to health monitoring, environmental monitoring, infrastructure monitoring, smart homes, and smart cars. Due to the varying environmental conditions under which these devices are expected to operate and to their large number, battery replacement has become a major concern. Recently, ultra-low power (ULP) systems-on-chip (SoCs) that can operate solely on harvested energy have been presented. A number of challenges face the dispersion of this technology: 1) reducing the power and energy consumption of the building blocks of these SoCs to stay within the budget of the energy harvester, 2) operating reliably under varying harvesting conditions, and 3) maintaining critical data in the event of a power loss. This work will investigate techniques to address these challenges and enable battery-less operation. One of the main techniques used to reduce power consumption is scaling the supply voltage (VDD) below the threshold voltage of the transistors (sub-threshold operation). Due to the quadratic dependence of power on VDD, reducing VDD to the sub-threshold domain will result in significant power savings thus enabling battery-less operation. However, with supply scaling comes the additional challenges of reduced reliability and performance. While performance is an acceptable trade-off in applications with low throughput requirements, ensuring reliability at low voltages remains a challenge. As VDD is scaled to the sub-threshold region, the on-to-off current ratio of a transistor is reduced, and the impact of process variations on its strength increases. These trends cause increased failures in ratio-ed circuits - such as the widely used static random access memory (SRAM) bit-cell - that depend on the relative strengths of their transistors for correct operation. SRAM cells are volatile in nature and thus lose their data when power is lost. However, they consume lower read and write energy than their non-volatile counterparts do. Emerging non-volatile cells such as spin-torque transfer RAM (STT-RAM) and ferroelectric RAM (Fe-RAM) have been introduced as replacements for the high power FLASH memories. While these cells consume significantly lower power than FLASH, their power consumption is still considerably higher than SRAMs which limits their use in battery-less devices. In this work, we will present an ULP battery-less IoT system-on-chip (SoC) with a non-volatile auto-recovery backup sub-system and highly optimized components to allow operation within a sub-uW power budget. Techniques are introduced within the SRAM instruction and data memories to improve their reliability and reduce their power consumption. A backup sub-system containing Fe-RAM arrays is also implemented to help the SoC recover in the event of power loss. A ULP voice activity detector is also developed as an always-on wake-up for the SoC. The combination of these techniques enable reliable battery-less operation of the SoC.
University of Virginia, Department of Electrical Engineering, PHD (Doctor of Philosophy), 2017
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PHD (Doctor of Philosophy)
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