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Low Power GPGPU Computation With Imprecise Hardware

Zhang, Hang
Format
Thesis/Dissertation; Online
Author
Zhang, Hang
Advisor
Lach, John
Abstract
Massively parallel computation in GPUs significantly boosts the performance of compute-intensive scientific and engineering applications due to improved floating point performance, but creates power and thermal issues that could limit further performance scaling. The high power consumption for general purpose computation in GPU (GPGPU) majorly comes from two sources: the memory system and the computation units, which can reach as much as 250W for high end GPUs due in large part to the sheer complexity of the IEEE-754 compliant hardware and its high activity factors during floating point operations. This thesis focuses on lowering GPGPU computation power consumption by using the imprecise hardware (IHW) methodologies. Imprecise Hardware is an emerging design paradigm that targets at high power computation units and seeks to improve power, area, latency, and related nonfunctional metrics through the use of quality tradeoffs in application domains that can tolerate relaxed correctness specifications. Power saving techniques such as dynamic voltage frequency scaling (DVFS) and power gating are capable of effectively reducing power consumption, but these approaches essentially trade-off between power and performance. The use of imprecise hardware (IHW) effectively shifts the design paradigm from a power-performance tradeoff to a power-quality tradeoff with little or no degradation in performance. The use of IHW is orthogonal to DVFS, power gating, and other hardware or software power optimization techniques, and can be combined with these techniques to further reduce the power consumption for GPGPU computation. This thesis demonstrates significant GPGPU power savings by relaxing application accuracy requirements and enabling the use of low power imprecise floating point and special function units, which are typically the most frequently exercised and the most power hungry arithmetic components in many high performance (high power) GPGPU computations. A set of novel imprecise floating point arithmetic units is presented and their non-functional metrics are obtained through post-layout SPICE level simulations. GPU performance simulator GPGPU-Sim and power-energy model GPUWattch are used to estimate the impacts of IHW units on output quality as well as the GPU system-level power consumption, providing a power-quality tradeoff framework for application-specific power optimizations on GPGPU platform. Experimental results in a 45nm process show up to 32% power savings with negligible impacts on output quality.
Published
University of Virginia, Department of Computer Engineering, MS (Master of Science), 2014
Published Date
2014-12-05
Degree
MS (Master of Science)
Collection
Libra ETD Repository
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